Study Guide for Final Exam

Here is a list of topics to study for the exam. You will find information on each topic in either your text (Chapter 5 and Appendix B), your class notes, or both.

• RAM design. (Be sure to check [my supplement]) -- this was not fully tested on the second exam.
• Review the instructions implemented in the Chapter 5 CPUs: lw/sw, R-type, beq, and j. Be sure you know exactly how the effective address is calculated for lw/sw, beq, and j.
• Single clock per instruction datapath and timing.
• Control signals for the single clock per instruction design.
• How to generate the control signals for the single clock per instruction design for each type of instruction. How to decode the fields of the instructions.
• Rationale for the multiple clock per instruction design.
• Tradeoffs in going to the multiple clock per instruction design: reduced number of hardware units; increased complexity of the control; speed advantage.
• State diagram for control of the multiple clock per instruction design.