| Office | NSB A-222 | ||||||||
| Phone | 997-3508 | ||||||||
vickery at babbage dot cs dot qc
dot edu
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| Office Hours | Tuesday and Friday, 1-2 PM | ||||||||
| Course URL | http://babbage.cs.qc.edu/courses/cs341
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| Required Text | Patterson, D. A., and Hennessey, J. L. Computer Organization & Design, Second Edition. Morgan-Kaufmann, 1998. ISBN 1-55860-428-6. [A list of errata for the first printing of the book (beige cover)]. [Get Acrobat Reader to read the errata]. Grading | (Percentages are approximate!) Homework
| 11.111%
| Exams 1 & 2
| 27.778% each
| Final Exam
| 33.333%
| | |
| Class No. | Date | Topics | Assignments |
| 1 | Feb 3 | Course Introduction and Scope Review of Computers and Programming | Chapter 1 |
| 2 | Feb 6 | Information Encoding; Performance Measurement | |
| 3 | Feb 13 | Performance Measurement and Calculation | Chapter 2 Homework 1 Due. |
| 4 | Feb 17 | Performance Measurement continued | |
| 5 | Feb 20 | MIPS Architecture | Chapter 3 Homework 2 Due. |
| 6 | Feb 24 | MIPS Machine and Assembly Language R and I Format Instructions | |
| 7 | Feb 27 | MIPS Machine and Assembly Language Branch and Jump Instructions | Homework 3 Due. |
| 8 | Mar 3 | MIPS Programming | |
| 9 | Mar 6 | Review | Homework 4 Due. |
| 10 | Mar 10 | First Exam Chapters 1-3 | |
| 11 | Mar 13 | Encoding Numbers Integers and IEEE-754 Floating-Point | Sections 4.1 through 4.4, and 4.8 |
| 12 | Mar 17 | Gates, Logic Networks, Truth Tables, and Logic Equations. | Appendix B.1 through B.3 |
| 13 | Mar 20 | Sum of products implementation. Karnaugh Maps. | Homework 5 Due. |
| 14 | Mar 24 | Decoders, Multiplexors, Adders. | |
| 15 | Mar 27 | Programmable Logic: PLA, PAL. | Homework 6 Due. |
| 16 | Mar 31 | PAL, PROM, parallel adder. | |
|
Mar 31 | Last Day to Drop Without Penalty | ||
| 17 | Apr 3 | Parallel ALU Design. Carry Lookahead Logic. | Chapter 4: Section 4.5. Homework 7 Due. |
| 18 | Apr 7 | Review for Exam. | |
| 19 | Apr 8 (Wed.) | Second Exam Chapter 4, Appendix B. | |
Spring Break April 10 -19 | |||
| 20 | Apr 21 | Sequential Circuits | Appendix B: Sections B.4 and B.5. |
| 21 | Apr 24 | Latches, Flip-Flops. | |
| 22 | Apr 28 | Register File Design. | [ Memory System Supplement ] |
| 23 | May 1 | Memory System Design. | Homework 8 Due. |
| 24 | May 5 | SRAM IC Design. | Chapter 5: Sections 5.1 - 5.3 |
| 25 | May 8 | MIPS Single Cycle Datapath. | Homework 9 Due. |
| 26 | May 12 | Generating Single Cycle Control Signals | |
| 27 | May 15 | Generating ALUop and Multiple Cycle State Control | Appendix B, Section B.6 |
| 28 | May 19 | Multiple Cycle Control Signals | Appendix C, Figures C.3, C.5, C.7 |
May 26 | ** FINAL EXAM ** | ||