This is the first semester CS-343 is being offered. Initially, the table below shows what material I plan to cover in the course, which you may use to get an idea of what we will be doing this term. But the sections in red give an impossibly short amount of time for each topic. As the semester progresses, I will update the table to show the actual assignments and due dates for this semester. As I update the table, I will change the background color from red to green. There is plenty of material to fill all those empty boxes!
| Class Number | Date | Topics and Assignments | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | September 4 | Course Introduction; review combinational logic.
Assignment 1 Due Memorize the Units of Measure and the Powers of Two Charts if you have not done so already. Review Appendix A through section A.10. | |||||||||
| 2 | September 9 | Sequential logic.
Read Section A.11 | |||||||||
| 3 | September 11 | Level and Edge Sensitive Circuits. | |||||||||
| September 16 | No Class (Yom Kipur) | ||||||||||
| 4 | September 17 (Tuesday follows Monday schedule.) | Finite State Machines
Read Sections A.12 and A.13 No Quiz | |||||||||
| 5 | September 18 | Finite State Machine Design
Read Sections A.14 and A.15 Assignment 2 Due Assignment 2 Solutions | |||||||||
| 6 | September 23 | Registers and Counters
Read / Review pages 99 through 120 | |||||||||
| 7 | September 25 | Serial Multiplier Design
Assignment 3 Due Assignment 3 Solutions | |||||||||
| 8 | September 30 | Serial Multiplier, continued
Multiplier Design Web Page Read Chapter 6 | |||||||||
| 9 | October 2 | Instruction Set Architectures
The Fetch-Execute Cycle | |||||||||
| 10 | October 7 | The ARC ISA
Arithmetic format instructions. AddCC vs. Add; Two's complement condition code logic, Carry/Overflow/Negative/Zero; Bitwise operations and ALU circuits to support them; Two's complement sign extension; using sign extension to place 13-bit immediate operands on the 32-bit B-Bus. The PC and IR registers; instruction fetch: IR <- Memory[PC]. Single clock cycle to transfer Rrs1 and Rrs2 to ALU, compute arithmetic or logic value, and return result to Rrd; ALU computes all values and uses multiplexors to select the correct one for the result. | |||||||||
| 11 | October 9 | *** First Exam *** | |||||||||
| October 14 | No Class (Columbus Day) | ||||||||||
| 12 | October 16
(Wednesday follows Monday schedule.) | ARC ISA: Load/Store/Sethi
| |||||||||
| 13 | October 21 | Exam 1 Post Mortem; expect to be tested on FSM
design again.
The ARC call instruction. Assignment 4 Due Assignment 4 Solution | |||||||||
| 14 | October 23 | ARC calls, branches, and jumps.
The ARC Datatpath design | |||||||||
| 15 | October 28 | ARC Register File Design | |||||||||
| October 30 | *** Last Day to Drop *** | ||||||||||
| 16 | October 30 | ARC Register File and ALU Design | |||||||||
| 17 | November 4 | ALU and Barrel Shifter; Lookup Tables
Microprogrammed Control Unit Design Microprogrammed CU relationship to Finite State Machine model | |||||||||
| 18 | November 6 | ARC Control Word fields. | |||||||||
| 19 | November 11 | ARC Control Word Sequences for ISA Fetch-execute cycle. | |||||||||
| 20 | November 13 | Microcode to execute ld and subcc
instructions.
Assignment 5 Due Assignment 5 Solutions | |||||||||
| 21 | November 18 | *** Exam 2 ***
During the exam, you will be provided with photocopies of some of the figures in Chapter 6. Click Here for a list of the figures you will get. | |||||||||
| 22 | November 20 | Memory Hierarchy; Memory operations.
Read Chapter 7 through page 268 | |||||||||
| 23 | November 25 | Exam Post Mortem
RAM Design: SRAM/DRAM; SRAM Binary Cell; SRAM IC; RAM Memory System. | |||||||||
| 24 | November 27 | Memory System Design | |||||||||
| 25 | December 2 | Cache Memory: Direct Mapped | |||||||||
| 26 | December 4 | Associative and Set-Associative caches
I/O System: Device Controllers Read Chapter 8 through page 313. 27
| December 9
| I/O System: Programmed I/O and Interrupt Processing
| Assignment 6 Due Assignment 6 Solutions (HTML) Assignment 6 Solutions (PDF) 28
| December 11
| I/O Busses: Asynchronous and synchronous
| Bus hierarchies
| December 17/19
| *** Final Exam ***
| Section 9MD3: December 17; SB B-145; 11:00 to 1:00
|
Click on the link above for information about the textbook for the course, how grades will be computed, the policy on homework, etc.
Click one of the links below to see what grades I have recorded for you so far this term. You need to send me a "codeword" to access your grades. See Homework Assignment 1 for details.
Grades become permanent two weeks after they are posted, so be sure to check your grades regularly to be sure there haven't been any mistakes.