Click on the link above for information about the textbook for the course, how grades will be computed, the policy on homework, etc.
Click the link below to see what grades I have recorded for you so far this term. You need to send me a "code word" to access your grades. See Homework Assignment 1 for details.
Grades become permanent two weeks after they are posted, so be sure to check your grades regularly to be sure there haven't been any mistakes.
Initially, the table below shows what material I covered in this course last semester, which you may use to get an idea of what we will be doing this term. Sections with a green background are accurate, but sections with a red background are tentative or incomplete. I will change the background colors as the semester progresses and the table is updated.
| Class Number | Date | Topics | Assignments |
|---|---|---|---|
| 1 | September 3 | Course Introduction; Units of Measure. | Memorize:
Units of Measure Powers of Two Review Appendix A through section A.10. |
| 2 | September 8 | Encoding audio information in binary.
| Read Section A.11
Assignment 1 Due |
| 3 | September 10 | Encoding visual information in binary: CRT images.
| Read Appendix B, pages 501-508 (minimization)
Review pages 469-470 (ripple-carry adder) Review Section 3.5.1, pages 76-78 (carry-lookahead logic) |
| 4 | September 15 | Review of Digital Logic Fundamentals: Encoding boolean values as voltages; noise margins; propagation delay (the time it takes a gate's output to change in response to changed value(s) at its input(s)); fan-in (the number of inputs to a gate); fan-out (the maximum number of loads to which an output may be connected while guaranteeing that the voltage on the output wire will not fall into the noise margin range. Truth tables, minterms, and constructing a sum of products network from a truth table. | Read Sections A.12 and A.13
Assignment 2 Due Assignment 2 Solutions |
| 5 | September 17 | Algebraic and Karnaugh Map minimization of combinational networks. Gate-input count as a measure of network complexity. Combinational building blocks: full-adder, multiplexer, decoder. | Read Sections A.14 and A.15 |
| 6 | September 22 | Combinational circuits compared to sequential circuits. Unclocked and clocked R-S latches. Synchronizing state changes with clock pulses. Clock pulse terminology: on time, rising edge, leading edge, falling edge, trailing edge, period, and frequency. Introduction to state diagrams; state changes (arcs) occur only when there is a clock pulse. | Read / Review pages 99 through 120
Assignment 3 Due Assignment 3 Solutions |
| 7 | September 24 | Latches (level-sensitive circuits) compared to
flip-flops (edge-sensitive circuits). Note that the textbook
explicitly uses "latch" and "flip-flop" interchangeably, which we do
not do in this course. For example, Figure A-46 in the text
is a latch, not a flip-flop. Use flip-flops whenever the
state must change no more than once per clock pulse. Three ways to
construct flip-flops are (1) create a short pulse at the edge of the
clock pulse using an AND gate and some buffers and/or inverters (not
recommended), (2) use two latches in a master-slave configuration
(Figure A-48 in the text), or (3) use the edge-triggered design
given in Figure A-52 of the textbook. Method 3 is "the standard"
but we will not cover it in detail in this course.
Registers and register transfers. Handel-C variables as register declarations. Handel-C par and seq blocks. | |
| 8 | September 29 | Flip-flop design: D and J-K compared.
Three-bit (modulo 8) up counter design. State diagram for three-bit up counter. Finite State Machine model: Combinational Logic, State Devices (latches and/or flip-flops) present state and next state connections; optional external inputs and external outputs. | Assignment 4 Due
Assignment 4 Solution Download and experiment with the Earle Latch. |
| 9 | October 1 | FSM controllers and sequence detectors.
Characteristic and Excitation Tables. Finite State Machine Models (Mealy and Moore), Using the Earle Latch in state machines and pipelines; state diagrams; state encoding ("encoded" or "one-hot"). | |
| October 6 | No Class (Yom Kippur) | ||
| 10 | October 7
(Tuesday) | Finite State Machine design example (modulo 4 up/down counter). State diagram, state table, excitation tables, minimizing the combinational logic functions, drawing the the circuit diagram for the complete machine. | |
| 11 | October 8 | *** First Exam ***
Last Semester's First Exam | |
| October 13 | No Class (Columbus Day) | ||
| 12 | October 15 | Multiplexer review: block diagram for; using a mpx with n-1 control inputs to implement any function of n variables; using multiplexers to implement multi-function registers; application of multiplexers to FSM design. Programmable Logic Devices: PLA, PAL, PROM, FPGA. Hardware configuration using fuses or a shift register setting the control inputs to multiplexers. Locations of fuse matrices in PLDs. | |
| 13 | October 20 | Schematic shorthand for fuse matrices; programming PLDs to implement logic functions. Number of gates and fuses in PLDs of various configurations; restrictions on number of minterms in PLAs and PALs. Using combinational logic as a read only memory (PROM). ROM, RAM, and WOM read/write operations. Two's Complement review: Negative weight of sign bit; sign extension. Programming logic functions using PLDs; number of gates and fuses in PLDs of various sizes; restrictions on number of minterms in PLAs and PALs. | |
| 14 | October 22 | The von Neumann Architecture: Input, Output, Instruction Memory, Operand Memory, Computation, Decision Making. Definition of RAM; same RAM used for Instruction Memory and Operand Memory (buffer overrun exploits). Central Processing Unit (CPU) provides Computation (ALU), Decision Making (control unit), as well as local storage (registers). Instruction Set Architectures (ISAs): complex = instructions that try to match high level language constructs, variable length instructions, many addressing modes (IBM S/370, VAX, Intel Architecture); reduced = fixed length instructions, simple memory accesses, fast clock traded off against more instructions per program (SPARC, PowerPC, etc.). The Fetch-Execute cycle as a FSM and expressed as an algorithm. | Read Chapter 6 |
| 15 | October 27 | The CPU datapath: registers, busses, and ALU. Propagation delays in the busses and ALU determine the maximum clock speed. Control Unit manages the datapath. Simple ALU design (Problem 6.1). | Assignment 5 Due
Solution |
| 16 | October 29 | Control Unit inputs (instruction register; clock; feedback from ALU; interrupt requests) and outputs (which registers go to A and B busses, which register gets result from C bus; ALU function code; memory read/write control). Design of a two's complement parallel adder/subtracter. Design of ALU. Computing Carry, oVerflow, Negative, and Zero condition code bits. | |
| November 3 | *** Last Day to Drop *** | ||
| 17 | November 3 | ALU design for the ARC Datapath, including condition code logic. | Assignment 6 Due
Solution |
| 18 | November 5 | Algorithms for instruction fetch and execution of addcc. Register-to-bus connection by means of multiplexers. | |
| 19 | November 10 | ARC Control Word Sequences for ISA Fetch-execute cycle. | Assignment 7 Due
Solution |
| 20 | November 12 | *** Exam 2 ***
Last Semester's Second Exam | |
| 21 | November 17 | ARC CPU Simulation: Classes ALU, Memory, Registers, and Register_Numbers. | |
| 22 | November 19 | ARC CPU Simulation: Classes IR and ARC_Simulator. | |
| 23 | November 24 | ARC CPU Simulation: Demo and code review. Control information needed for each clock cycle. Implementation of bus control logic. | |
| 24 | November 26 | Microprogrammed Control Unit design: Fetch, decode, addcc. Microinstruction fiedls. Selecting the next microinstruction; the cond and jump address fields. | Assignment 8 Due
Solution |
| 25 | December 1 | Microprogrammed Control Unit design continued. The st control sequence. Counting clock cycles for microcode control sequences. | |
| 26 | December 3 | Microprogrammed control unit design compared to state machine design. | |
| 27 | December 8 | Memory Hierarchy; cache concepts; bandwidth; bus hierarchy; I/O system concepts. | |
| December 10 | Polled and Interrupt Driven I/O with a UART device controller. | Assignment 9
Solution | |
| December 18 | *** Final Exam ***
11:00am to 1:00 pm, SB-141 Last Semester's Final Exam | ||