CS-343 Assignment 6

Write out the answers to the following questions and email them to me by midnight, November 18.

1. Define the following the terms in the context of pipelined CPU design:
   • depth
   • latency
   • throughput
   • bubble
   • stall
   • structural hazard
   • data hazard
   • control hazard
   • reordering
   • result forwarding
   • delayed branch
   • prediction
   • speculative execution
2. A processor uses a 1 GHz clock with no pipeline. If it is redesigned to use a 5-stage pipeline,
   • Ideally, what would the clock rate change to?
   • Ideally, what would be the performance of the pipelined processor compared to the non-pipelined processor?
3. Tell the widths and contents of each of the pipeline registers in Figure 6.27.
4. There is an error in Figure 6.30, and the same error is repeated in Figure 6.32. What is it?