Overview
For this assignment, you are to use the Altera Quartus II design software and an Altera UP2 development board to implement a combinational logic circuit. When the assignment is working, you will be able to turn four switches on and off to produce a 4-bit binary number and see the hexadecimal representation of the binary number on a seven-segment display.
Procedure
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Log into your account and verify that it is working correctly.
Log into any one of the computers in A-205 or A-227 using your account name for this course, which consists of the first letter of your first name, your last name, and the digits "343" all as a single lower-case string. That is, if your name is "Always A. Good Student", your account name is astudent343. Use the password given to you in class, and remember that you will be required to change it to something secure the first time you log in.
The names of the computers are:
A-205 A-227 birch apple cherry fir chestnut juniper elm mimosa ginkgo peach hemlock pine hickory plum spruce sycamore walnut Use Windows Explorer to verify that your ’My Documents’ directory contains a directory named ’My Projects.’ Create a new directory named ’Assignment_01’ in your My Projects directory. The new directory must be spelled and capitalized exactly as shown, including the underscore character, in order to receive credit for this assignment!
Log off the computer you used and log into another one. Verify that your Assignment_01 directory shows up on the second computer, indicating that your settings were successfully copied to the domain server (maple) when you logged off the first computer and that they were then copied to the second computer when you logged into it. If you have any problems with this step, contact Dr. Vickery for help before proceeding with the assignment.
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Create a Quartus project for the assignment.
Start the Quartus II application by clicking the icon on the desktop. If you see any messages referring to software licenses, there is a problem. You can try to fix it selecting ’specify license file’ or by going to Tools->License Setup and specifying @oak.cs.qc.edu as the location of the license file. If that doesn’t work, report the problem to Dr. Vickery and try another computer. Do not select the 30-day trial option, web license update, or any of the other possible choices offered to you; that would just mess things up.
From the File menu, run the New Project Wizard. Select your Assignment_01 directory when asked where the project goes, and give the project the name bin2hex. Spell it just like that.
You can skip the step that asks for design files to add to the project. I am supplying you with one, but you can add it later.
On the family and device settings step, select FLEX10K for the family and EPF10K70RC240-4 for the actual part number. This corresponds to the actual FPGA device on the UP2 development board you will be using.
Skip the EDA tool settings step, and click Finish when the wizard shows the summary of the project.
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Create a logic circuit.
From the File menu (or by clicking the new page toolbar button), create a new Block Diagram/Schematic file. Use the Symbol Tool (the button that looks like an AND gate) to add four input pins and seven output pins to the circuit. Look under Libraries->Primitives->pin when the Symbol panel opens up to find the pin symbols. Name the input pins IN_1, IN_2, IN_4, and IN_8. Actually, you can name them anything (meaningful) you want to, but those are the names used in this assignment page. Likewise, name the output pins Segment_A, Segment_B, etc. or something similar. Use the “Orthogonal Node Tool” (the one for drawing wires) for connecting the four inputs to the first four outputs. Connect the other three outputs to the fourth input too.
You might find it helpful to turn on the Show Gridlines option under the View menu. If you make mistakes, select the wire piece you don’t want and delete it using the Del key. You might want to zoom in (Control-Spacebar) to do accurate work. Once a wire is connected to a pin, you should be able to move the pin and the wire will stay connected; that’s a way to make sure your connections are good.
Save your circuit and compile it. At this point, your circuit is probably named Block1.bdf. Save it (Control-S, or File->Save, or click on the floppy disk toolbar button), and when prompted for the name, say bin2hex. This name must exactly match the name specified as the project name earlier. Now do a first compilation of the diagram: select Tools->Compiler Tool->Start or click the toolbar button with the right-pointing triangle on it (next to the grayed out Stop button, or just type Control-L.
Four tools should run: Analysis & Synthesis, Fitter, Assembler, and Timing Analyzer. There should be no errors and no warnings.
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Make the pin assignments.
You have to tell Quartus which pin numbers on the FPGA correspond to the input and output pins in your diagram. Use the second item (Pins) on the Assignments menu. When the big panel opens up you will see an empty table with the first two columns named To and Location. The first row should have two green items named <<new>>. If you double click on the left one, you should get a drop down menu of the pin names in your diagram. Click on the first one to select it, and go to the next column. There, you can either select the pin number from a drop-down list, or just type in the pin number.
Here are all the pin connections on the UP2 that you will be using in this course (not just this assignment):
Connection Pin Name Switch 1 PIN_41 Switch 2 PIN_40 Switch 3 PIN_39 Switch 4 PIN_38 Switch 5 PIN_36 Switch 6 PIN_35 Switch 7 PIN_34 Switch 8 PIN_33 Left Digit, Segment A PIN_6 Left Digit, Segment B PIN_7 Left Digit, Segment C PIN_8 Left Digit, Segment D PIN_9 Left Digit, Segment E PIN_11 Left Digit, Segment F PIN_12 Left Digit, Segment G PIN_13 Left Digit, Decimal Point PIN_14 Right Digit, Segment A PIN_17 Right Digit, Segment B PIN_18 Right Digit, Segment C PIN_19 Right Digit, Segment D PIN_20 Right Digit, Segment E PIN_21 Right Digit, Segment F PIN_23 Right Digit, Segment G PIN_24 Right Digit, Decimal Point PIN_25 Button 1 PIN_28 Button 2 PIN_29 It will make most sense if you use Switch 5 as IN_8, Switch 6 as IN_4, etc, and I suggest using the right digit of the two seven-segment displays. After you have made the pin assignments, you can save yourself a mouse click by by typing Control-S to save the settings without being asked to do so later.
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Recompile the design and configure the FPGA.
You had to compile the design once so the Assignment Editor could tell what pins you are using, and now you have to compile it again to get the assignments into the configuration file for the FPGA. Just press Control-L again to recompile.
Make sure the UP2 is connected to the parallel port of the PC you are using through a ’Byte Blaster’ cable., and connect the power cube to the DC_IN connector on the UP2; two green LEDs should light up. Go to the Programmer panel. It’s the rightmost button on the top toolbar, or you can get to it using the Tools menu. If you don’t see “Byte Blaster [LPT1]” near the top of the panel that comes up, click the Hardware Setup button in the top left part of the panel and select it from the drop down menu.
In the Programmer panel, you should see a table with one row with the name bin2hex.sof in the File column. Click the box in the Program/Configure column for that file, and click the Start button on the left side of the panel. After a few seconds, all seven segments and the decimal point of the left seven segment display should light up and, assuming all of switches 5-8 are up (off), just the decimal point on the right seven segment display should be on. Operate the switches to verify that closing switch 8 turns on Segment A, switch 7 turns on segment B, etc. Remember, IN_8 (switch 5) should control all of segments D, E, F, and G at this point.
It would be a good idea to exit Quartus and log off the computer at this point as a way of saving your work so far.
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Generate Hex Digits on the seven segment display.
So far this assignment has had precious little ’logic’ in it’ ’logic design.’ True, a wires meet the definition of combinational logic. If you know the logic values put into them you know the logic values coming out, but it’s time to try something useful. But what we need, a network that converts four-bit binary numbers into settings to turn the elements of a seven segment display on and off gets a bit tedious to design and build. So I’m providing the design to you, in the form of a program written in a Hardware Description Language (HDL) called Verilog. I’ve put the code in a separate file so you can just download it into your project instead of doing a cut and paste from this web page. So start, using a computer in the lab, by right clicking on that link and saving the file in your Assignment_01 project directory. (Update: with the release of Assignment 2, the link is to a file named hex2sevenseg_with_error.v. To work on this assignment, you need to download this file to your Assignment_01 directory and rename it to hex2sevenseg.v.)
Add the Verilog module to your project by using the Project->Add/Remove Files in Project menu. Then open the file for editing using the File->Open menu (Control-O). With the file open, convert it to a Symbol file using the File->Create/Update->Create Symbol Files for Current File menu item. There should be no errors or warnings.
Now go to your schematic diagram (bin2hex.bdf) and delete all the wires. Click on the Symbol tool (the AND gate) and you will now see a new Library named Project which, when you open it, will contain hex2sevenseg. Insert a copy of that symbol into your schematic, connect the input pins to the input of the symbol, and connect the outputs of the symbol to the output pins of your circuit. Recompile and download the new configuration to the UP2. Verify that the right seven segment display shows the hexadecimal representation of the state of switches 5-8.
But it doesn’t look right! Congratulations, you’ve discovered that the Verilog program I gave you is wrong!! (If you already looked at the code, you knew this was coming.) Your task now is to construct the truth table for the erroneous function (segment G) and, using the other six functions as a model for how to write a logic equation in Verilog, to fix the program, reconvert it to a symbol, recompile your design (no need to remove and reinsert the symbol, just recompile), and download your corrected design to the UP2 board. Verify that all sixteen combinations of input settings for the switches produce the correct pattern of lights in the seven segment display.
Optional: Connect the other four switches to the other seven segment display through another hex2sevenseg symbol.
Exploring Other Things: If you run the RTL Viewer from the Tools menu, and click on the hex2sevenseg symbol, you can see what logic network the Verilog program was compiled into. Use Control-Spacebar to zoom in. If you run the Technology Mapper from the Tools menu, you can see what kinds of building blocks on the FPGA were used to implement different parts of the design, and if you run Timing Closure Floorplan from near the bottom of the Assignments menu, you can see how your pins and logic elements were mapped on to the actual FPGA. Again, zoom in to see details. Click the “Show Node Fan-In” and “Show Node Fan-Out” buttons on the left of the diagram to see how I/O pins are connected to logic elements; click on colored squares in the middle (zoom in to see them if necessary) to see where different parts of the design were placed on the chip.
Be sure to exit Quartus and log off the computer so you work is saved back to maple when you are finished.
Submit the Assignment
When you have completed the assignment, send me an email message telling me the project is ready for grading. I will get a copy of it from maple and test it.
If you worked on the assignment with someone else, be sure to list the names of both contributers in the email message so you both get full credit. Be sure to tell me which account has the final version of the project for me to look at.
Remember, it is perfectly all right to help each other to do the assignment. Just don’t exchange design files with each other; nobody learns anything if you do that.
Due Date The assignment is due by midnight, September 19. Do not submit the assignment unless you have verified that it works correctly using an actual UP2 in the lab. Having said that, you can get partial (half) credit for “trying.” Just say in your email that the assignment is incomplete, and I will look at your project, but not try to run it.