Overview
You have the option of working on an ambitious extra-credit assignment for the course: implementing the single-cycle processor from Chapter 5 on the Altera DE-1 logic kit. I will provide you with a top-level design schematic, and your job will be to implement each of the custom symbols in that schematic.
I encourage you to work with a partner on the project, but you may not work in a group with more than two people in it. On the other hand, feel free to help others out, to post and answer questions about the assignment on the course discussion board, and to ask me questions.
Contrary to what I said in class when I first announced this assignment, your grade on the project will substitute for your lowest exam score in the course. However, if your grade on the project is lower than your lowest exam score it will not count against you.
Because the project is complex, there are some ground rules to follow:
- If you plan to work on the project, you must decide to do so right away, and you must start work on the project immediately. Send me an email by April 18 telling me if you plan to attempt the assignment. If you are going to work with a partner, tell me whose account you will be using for doing the work. On Friday of each week between now and the due date, I will look at your project directory to evaluate whether you are making satisfactory progress or not. You will receive no credit for the assignment if you do not show evidence of working on it systematically each week.
- You will have to work from my top-level design file, which is described below.
- You must develop the project systematically, following the steps outlined below in the order given. At the end of each week, send me an email telling me which step you are working on; I will check that you have completed all previous steps correctly.
- Careful testing of each stage of the design is a crucial part of the development process.
- You do not have to complete the entire design to receive a passing grade for the assignment.
Project Scope
The project has both limitations and added features compared to the processor designed in the textbook. The two main limitations have to do with the implementation of the instruction and data memories. I will supply you with complete Verilog implementations of both.
The instruction memory has room for just 64 instructions, with their values hard-coded into Verilog assignment statements. To test your design fully, you will need to try various sequences of instructions. You can use the MIPS simulator that comes with the textbook to translate assembly language programs into hexadecimal codes, which you can then cut and paste into the Verilog assignment statements to initialize your instruction ROM.
The data memory is implemented using the SRAM (static RAM) chip on the DE1 kit, which limits its size to 512KB instead of 4GB.
The textbook design has to be expanded to incorporate immediate instructions in order to be able to test it. The problem with the textbook design is that none of the instructions included will produce non-zero values that you could examine to tell whether anything is happening or not. There are some other possibilities for dealing with this problem, but implementing immediate instructions is not hard and makes it possible to generate useful test programs more easily.
Top Level Design
The top-level design has to manage all the I/O for the design, and to provide the infrastructure for debugging the project as you go along.
Key_0, the rightmost of the four pushbuttons on the DE1, is used as the CPU clock for the system. The idea is that you will manually generate each clock pulse by pressing Key_0 so you can check everything out before generating the next one.
The four seven-segment displays show the status of various parts of the system. The following values can be displayed:
- 3'b000:
- Current Program Counter (PC)
- 3'b001:
- Current Instruction
- 3'b010:
- Read Data 1 (Rrs)
- 3'b011:
- Read Data 2 (Rrt)
- 3'b100:
- ALU Result
- 3'b101:
- Debug (branch target address)
- 3'b110:
- Data Memory data out
- 3'b111:
- Control Signals
The three pushbuttons, Key_3, Key_2, and Key_1 are used to select which value is to display. Since the four seven-segment displays can only show 16 bits of information at a time, the leftmost slide switch (SW_9 selects whether to show the rightmost 16 bits (when the switch is towards the edge of the DE1 board) or leftmost 16 bits (when the switch is towards the hexadecimal displays) of the value selected with Keys 3:1. There are only ten control signals, so SW_9 has no effect when displaying them.
There are ten control signals. The following table shows the order in which they are displayed when you select 3'b111 with Keys 1-3:
| Name | Bit Position | Hex Display |
|---|---|---|
| RegDst | 9 | 0200 |
| Jump | 8 | 0100 |
| Branch | 7 | 0080 |
| MemRead | 6 | 0040 |
| MemtoReg | 5 | 0020 |
| ALUOp[1] | 4 | 0010 |
| ALUOp[0] | 3 | 0008 |
| MemWrite | 2 | 0004 |
| ALUSrc | 1 | 0002 |
| RegWrite | 0 | 0001 |
There are ten red LEDs and eight green LEDs on the DE1 that you are free to use in any way you please. In the top-level design I am providing, they are connected to various slide switches and control unit outputs; you will probably want to connect them to various parts of your design as you debug different sections.
Development Steps
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Download the Quartus Project that I am supplying and test it.
Click on the link to download the Zip file that I am providing, and unzip it into your My Projects directory, where you will get a Quartus project in a directory named Single_Cycle_Datapath. The project is complete, so you should be able to open the project by double-clicking on the project file, single_cycle_datapath.qpf.
There will undoubtedly be updates to the Zip file.
The timestamp of the current version is Sun, 09 Jul 2023 19:14:13 -0700.Date Changes April 19 Original Version April 20 - Bug Fix: Control unit was not recognizing op codes properly.
- Test program now lets you see the results of memory read operations.
- Changed name of files named CPU_Register.xxx to PC_Register.xxx.
Download the programming file, single_cycle_datapath.sof to a DE1 kit, and step through the sample code provided to be sure you understand how to work with the buttons and switches, and how to interpret the values displayed on the seven segment displays and the LEDs.
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Optional: Use PC SPIM to run a test program.
PC SPIM is a simulator of the MIPS processor that came on the CD accompanying the textbook. You can also download it from www.cs.wisc.edu/~larus/SPIM/pcspim.zip.
You can write a MIPS assembly language program using any text editor, load it into the simulator, and single step through it to verify that it does what you expect. Then, you can save the state of the simulator in another text file (normally called PCSpim.log), and use that to update the contents of the ROM in instruction_memory.v.
You need to set the following options in PC SPIM, which you can do from the program’s menu item: turn on “Save window positions,” “General registers in hexadecimal,” “Delayed Branches,” and “Allow pseudo instructions;” turn off “Bare machine” and “Load exception file.” The other options don’t matter.
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Implement the Program Counter
The zip file I provided contains a file named PC_Register.bsf, which is the symbol for the Program Counter. My Verilog implementation of that symbol is in a file named PC_Register.v. Your job is to add a new block diagram file to the project named PC_Register.bdf and to implement the same functionality as the Verilog program in that schematic diagram file. That is, you will need 32 flip-flops that get loaded each time CPU_Clock goes true. To get you started, I built a skeleton version of PC_Register.bdf and left it in the project directory. You can simply add that file to the project and remove PC_Register.v from the project (without actually deleting the .v file from the disk if you want to keep it) using the menu item.
Be sure to test your project carefully with your version of the PC in place before proceeding to the next step.
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Implement the Register File
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Implement the ALU
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Implement the Control Unit
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Implement the Multiplexers