Solution

  1. Compute the minimum-allowed and average clock cycle periods for the single-cycle and adjustable clock designs.
    Book: 400 × 0.45 + 600 × 0.25 + 550 × 0.10 + 350 × 0.15 + 200 × 0.05 = 447.50 psec A-6: 415 × 0.43 + 665 × 0.30 + 620 × 0.07 + 370 × 0.17 + 250 × 0.03 = 491.75 psec
  2. Compare the performance ratio of the two designs with the values computed in the textbook. State which design is faster and by how much for the fixed and variable period clocks.
    Book: 600 ÷ 447.5 = 1.34; the variable-period design is 34% faster than the fixed-period design. A-6: 665 ÷ 491.75 = 1.35; the variable-period design is 35% faster than the fixed-period design.

    665 ÷ 600 = 1.108; the fixed-period design in the book is 10.8% faster than the fixed-period design from Assignment 6.

    491.75 ÷ 447.5 = 1.099; the variable-period design in the book is 9.9% faster than the variable-period design from Assignment 6.

  3. Would the new paremeters given here increase or decrease the clock speed attainable in the multicycle design to be developed in the second part of Chapter 5? And how much faster would the clock be using the values from the book compared to the ones given here? Remember, in the multi-cycle design, the clock period has to be long enough to accommodate the slowest part of the datapath: the memory units.

    The maximum clock speed for the design in the book would be determined by the propagation delays in the slowest unit: 200 psec for the memories. So the maximum clock speed would be 1 ÷ (200 × 10-12) = 0.005 × 1012 = 5.000 × 109 = 5 GHz.

    The maximum clock speed for the design in Assignment 6 would also be determined by the propagation delays in the memories: 250 psec in this case. So the maximum clock speed would be 4 GHz. The book’s design would be 5 ÷ 4 = 250 ÷ 200 = 1.25 times faster than the design from Assignment 6; a speedup of 25%.