CS-343 Final Exam Review Guide

What This Is

The exam will cover material from Chapters 2, 4, 5, 6, and Appendix B of the textbook, plus material based on assignments using the Altera DE1 logic kits. But not everything from all chapters will be covered, so the list below gives you topics that are sure to be on the exam. I apologize if I left anything out (anything we covered in class is “fair game” for the exam), but the list should give you a good idea of what to concentrate on as you review for the exam. If a topic from the book was not covered in class and is not mentioned below, you do not need to worry about it.

The List

• MIPS ALU design and implementation
• MIPS Register File design and implementation
  • Number of ports
  • Widths of register number inputs and register data inputs/outputs
  • Implementation of Register 0
  • Operation of the DE1 Testbed for the register file project
• MIPS Machine Language: The fields in each of the three instruction formats, and the three uses for I-Format instructions.
• MIPS memory structure; byte and word addresses.
• Calculating Branch and Jump target addresses.
• Calculating lw and sw effective addresses.
• The lui instruction.
• Single-cycle CPU design
  • PC Address calculation
  • Jump Address calculation
  • Control of Register File inputs
  • Generating immediate operands
  • Control of ALU input sources
  • Effective Address calculation
  • Writing the correct result, if any, to the Register File
• Performance of the single-cycle design
  • Calculating the execution time of a program
  • CPI for the single-cycle design
  • Clock period for the single-cycle design: analyzing propagation delays for instruction types
  • Comparing the performance of two designs by comparing execution times
  • Comparing fixed-period single-cycle design to hypothetical variable-period design
    • Why the variable-period design is hypothetical
    • Using average CPI, weighted by instruction-type frequencies, for the variable-period design
    • Calculating performance ratios: “times faster” and “percent faster”
• Implementing the single-cycle design
  • Using the DE1 testbed for the single-cycle design
  • Features tested by various instructions and instruction sequences in the sample program
• Multi-cycle CPU design
  • Rationale for the multi-cycle design
  • Registers added to the multi-cycle design compared to the single-cycle design; why they are needed
  • Combinational logic units removed from the multi-cycle design compared to the single-cycle design; why they are not needed.
  • Figures 5.37 and 5.38
  • Computing CPI and clock period for multi-cycle design
  • Comparing performance of single-cycle and multi-cycle designs: why multi-cycle design is not better
• Pipelined processor design
  • Terminology: stages, pipeline registers, latency, throughput, balance, bubbles/stalls
  • Ideal speedup in a perfectly balanced pipeline with no stalls
  • Contents of the pipeline registers for each stage
  • Number of stages and number of pipeline registers for the MIPS design in the book
  • Hazards: data and control dependencies
  • Register forwarding
  • Delayed load and delayed branch