Introduction
The second exam will test material covered since the first exam. This test will not re-test you on material from the first test, but it will often assume that you remember that material.
Since the last exam, we have covered at least parts of the following sections from Appendix B of the textbook: B.7, B.8, B.10, B.11, and B.12. Much of the exam will be based on what was covered in class and on the two logic design assignments (MIPS ALU and Up/Down Counter).
Topics
- Quartus implementation of the MIPS ALU
- Quartus implementation of the Up/Down Counter
- Finite State Machine (FSM) model
- Mealy and Moore outputs
- State Diagrams (circles and arcs)
- State Table construction and implementation
- Difference between combinational and sequential circuits
- Level-sensitive flip-flop (latch) gates and operation
- Edge-triggered flip-flop gates and operation
- Why level-sensitive circuits are not appropriate for FSM implementations
- Use of Clock, ENA, PRN, and CLRN inputs of Quartus dffe elements
- PRN and CLRN as asynchronous inputs
- You do not need to know how to draw the gates for a dffe with PRN and CLRN, but you do need to know how to draw the gates for an edge-triggered D flip-flop with ENA.
- Register structure and implementation
- Register file structure and implementation
- Datapath structure: connections between ALU and Register File
- Definition of “memory port”
- Definition of “clock skew” and how ENA inputs to flip-flops eliminates it
- Memory operations (read and write) as they apply to a register file
- Number of input and output wires of the MIPS register file, the MIPS ALU, and the MIPS datapath, and where these numbers come from or go to
- Implementing RegWrite in the MIPS register file
- How Register 0 is special and how to implement it in the MIPS register file
- How to build a 32 × 32 multiplexer (or any other × n mux)
- How to use a decoder to control the ENA inputs of the MIPS registers
- How data wires for ALU result connect to the data inputs of the registers in the MIPS register file
- This list might be incomplete.