Disclaimer

Everything listed here is “fair game” for the exam, but I cannot guarantee that I haven’t forgotten something here that just has to be included on the exam. If in doubt, ask on the Course Discussion Board.

Reading Assignments

  1. All material from Exam 2.
  2. Figure 4.17: the role played by each element and control signal in the execution of R-type, lw/sw, and beq instructions.
  3. The rationale behind pipelining
  4. Compare single-cycle and pipelined performance
  5. What is a balanced pipeline; what determines the clock speed of a pipelined processor.
  6. Figure 4.51: the role played by each element and control signal in the execution of R-type, lw/sw, and beq instructions; the control and data information in each pipeline register
  7. Structural, Data, and Control hazards
  8. Register forwarding concepts and implementation
  9. Spatial and temporal locality: what makes the memory hierarchy “work”
  10. Hit and miss ratios: calculating the effective (average) memory latency (access time)
  11. Definitions of cache lines, memory blocks; tag, index, block offset, word offset fields of an address
  12. Compute widths of address fields given cache configuration parameters, and vice-versa
  13. Set-associative cache design; address field sizes with different set sizes
  14. Definitions of write-through and write-back
  15. DRAM compared to SRAM with respect to capacity, latency, and cost per bit; relate to memory hierarchy principles
  16. Disks: platters, surfaces, read/write heads, tracks, cylinders, sectors
  17. Disk latency components and how to compute them
  18. I/O busses and controllers