Summary

Do a timing analysis of the single-cycle datapath developed in Chapter 4 of the text.

Specifics

Figure 4.24 on page 329 is a diagram of the complete MIPS single-cycle datapath that you are to analyze. The goal is to determine the maximum clock speed that can be used, given some knowledge about the propagation delays of the various components of the datapath.

Not to give away the answer, but we know that the worst-case number of propagation delays will be for lw instructions because they require the longest sequence of operations to complete (fetch the instruction, read from the register file, compute the effective address, read from data memory, and write back to the register file.) For this assignment, you are to do a detailed analysis to determine just how long this critical path will take. And to be sure we are right about lw being the critical instruction, you are to analyze branch, jump, and R-Type instructions too.

Assumptions

The following table shows the propagation delays we will work with for all the elements in Figure 4.24, in picoseconds.

Elementpicoseconds
Multiplexer10
Adder100
Memory Read100
Memory Write100
Register file Read100
Register file Write100
PC read10
ALU200
Shift0
Sign Extend0
Control50

And here is a version of Figure 4.24 with the above values marked in in red: marked up diagram>

Notes: Combine the jump and branch multiplexers in the upper right side of Figure 4.24 into one multiplexer, as shown in class. Assume the main control unit and the ALU control each take 50 psec.

Start each analysis with the edge of a clock pulse that loads a new value into the PC.

Write out the answers to all the following questions:

Analysis Procedure: Jump

  1. How long does it take to fetch the instruction?
  2. How long does it take the Control Unit to decode the instruction and set the Jump control signal?
  3. Which takes longer: calculating PC+4 or fetching the instruction from Instruction Memory?
  4. When is the Jump Address valid?
  5. When would it be safe for the next clock pulse to occur?

Analysis Procedure: Branch

  1. How long does it take to fetch the instruction?
  2. How long does it take the Control Unit to decode the instruction and set the Branch control signal?
  3. When is the Branch Target Address valid?
  4. When is the A operand to the ALU valid?
  5. When is the B operand to the ALU valid?
  6. When is the function code input to the ALU valid?
  7. When is the Z output of the ALU valid?
  8. When would it be safe for the next clock pulse to occur?

Analysis Procedure: R-Type

  1. How long does it take to fetch the instruction?
  2. How long does it take the Control Unit to decode the instruction and set the ALUSrc control signal?
  3. When is the A operand to the ALU valid?
  4. When is the B operand to the ALU valid?
  5. When is the function code input to the ALU valid?
  6. When is the ALU result valid?
  7. When is the WR Reg input to the register file valid?
  8. When is the Write Data input to the register file valid?
  9. When would it be safe for the next clock pulse to occur?

Analysis Procedure: Store

  1. How long does it take to fetch the instruction?
  2. How long does it take the Control Unit to decode the instruction and set the ALUSrc control signal?
  3. When is the A operand to the ALU valid?
  4. When is the B operand to the ALU valid?
  5. When is the function code input to the ALU valid?
  6. When is the ALU result valid?
  7. When is the MemWrite control signal valid?
  8. When would it be safe for the next clock pulse to occur?

Analysis Procedure: Load

  1. How long does it take to fetch the instruction?
  2. How long does it take the Control Unit to decode the instruction and set the ALUSrc control signal?
  3. When is the A operand to the ALU valid?
  4. When is the B operand to the ALU valid?
  5. When is the function code input to the ALU valid?
  6. When is the ALU result valid?
  7. When is the MemRead control signal valid?
  8. When is the WR Reg input to the register file valid?
  9. When is the Write Data input to the register file valid?
  10. When would it be safe for the next clock pulse to occur?

Final Analysis

What is the longest clock period needed for any instruction?

What is the maximum clock frequency that could be used?

Submit The Assignment

Write your answers in the body of an email message (do not send an attachment), and send it to me by midnight of the due date.

Send me email (vickeryatbabbage.cs.qc.cuny.edu) with “CS-343 Assignment 5” as the subject. Be sure to put your name in the body of your message.