CS-343 Assignment 3

We are still working in Sections 1-5 of Appendix C of the text. Section C.4 (Verilog) will not be important until after we finish the rest of Appendix C, so you do not need to study that section carefully now. But do read it over. The next assignment after this one will be to implement the full MIPS ALU (but only four bits wide), so Section C.5, which covers that design, is important.

Minimization is mentioned, but not covered. in the text. For that topic, read my web page on Minimizing Boolean Functions.

Remember, the first midterm exam is scheduled for March 2. It will cover all the material listed above, and the material from Assignments 1-4.

Create a directory named Assignment_3 under your My Projects directory in the TREE lab. Copy your full adder block diagram file and block symbol file from Assignment 2 into the Assignment 3 project directory. (Some people used additional modules to implement their full adder in Assignment 2; if you did, copy those to Assignment_3 too.)

Download a Verilog module I am supplying, hex2sevenseg.v, and save it in the project directory also.

Now use the Quartus New Project wizard to create a new project in your Assignment_3 directory. Name the project “four-bit_adder-subtracter” (remember, there must be no spaces in the project name). Name the top-level design module Assignment_3_Testbed (again, no spaces). When the wizard asks you to add files to the project, select the “add all” option to add your full adder and my Verilog module to the project. The rest of the project settings will be the same as for Assignment 2.

Create a block diagram file named four-bit-adder-subtracter.bdf. Use four instances of your full adder symbol to implement this module. Label the input pins A[3..0], B[3..0], and sub. Label the output pins Sum[3..0], Cout, and Overflow. When the sub input is false, the circuit is to operate as a four-bit adder, but when sub is false, the circuit is to negate the B bits (use XOR gates for this) and add 1 by making Cin to the rightmost full adder true.

Save this block diagram as a symbol.

Create the testbed module for the assignment in a block diagram file named Assignment_3_Testbed.bdf. Set up input pins named Switch[8..0], and output pins namedRed_LED[8..0], Hex_1[6..0], and Hex_0[6..0].

Convert hex2sevenseg.v to a symbol, and insert two copies of it into the testbed. Connect the outputs of one to the Hex_1 pins, and the outputs of the other one to the Hex_0 pins.

Add one instance of your four-bit-adder-subtracter to the testbed.

Connect the 9 switches to the corresponding Red LEDs. Connect the four sum outputs of of the adder-subtracter to the four inputs of the Hex_0 seven segment display decoder. Connect Cout from the adder-subtracter to input #3 of the Hex_1 seven segment display decoder, connect the Overflow output to input #2; connect ground to inputs 1 and 0.

Testbed Pin	four-bit-adder
Switch[8]	sub
Switch[7..4]	A[3..0]
Switch[3..0]	B[3..0]

Make the DE1 pin assignments for the testbed pins. The DE1 I/O Pins web pages calls the segments A-G, which correspond to pin numbers 0 through 7, respectively. Test your four-bit adder-subtracter, and fix it if it doesn’t work. Be sure the carry and overflow values are correct as well as the sums and differences for various values of A and B.

When you have built, tested, and debugged your assignment, be sure to log out of your account so the project will be copied back to the server. Then send me an email at vickeryatbabbage.cs.qc.cuny.edu by midnight of the due date to tell me the assignment is ready. I will copy the project from the server to my computer for testing.

The only way to submit the assignment is to put it in the proper profile subdirectory of your TREE lab account.

The Subject line of your email message must be: “CS-343 Assignment 3.”