CS-343 Assignment 9

This assignment is based on the second part of Chapter 4 of the textbook: pipelining.

Write out the answers to the following questions:

1. If a single-cycle processor design has a clock frequency of F, what would be the optimal speedup if the design is converted to a pipelined design with n stages?
2. Define instruction latency and instruction throughput. Read the next two questions before answering this one.
3. What is the relationship between latency and throughput for a single-cycle processor design?
4. What is the relationship between latency and throughput for a pipelined processor?
5. What is a perfectly balanced pipeline?
6. A ten-stage pipeline has the following maximum propagation delays in each stage (in psec): 50, 55, 45, 57, 49, 54, 48, 47, 2, and 2000. What would be the maximum clock speed at which this processor could operate?
7. For the previous question: what would be the instruction latency of the processor? Be sure to indicate both the numerical value and the proper unit of measure.
8. For the above pipeline, what would be the instruction throughput of the processor, assuming there are no hazards?
9. If it was your job to improve the design of the above pipeline design, what would you try to do?
10. Define structural, control, and data hazards. Read the next question before answering this one.
11. Give an example of each of the three types of hazards listed above.
12. For each of the following terms, tell which of the three typess of hazard it is designed to deal with, and tell briefly how it does so.
    • delayed branch
    • delayed load
    • register forwarding
    • branch prediction
13. For each of the four pipeline registers in Figure 4.51 on page 362, note that there is a certain number of arrows going into each one: 2 into IF/ID; 9 into ID/Ex; 7 into EX/MEM; and 4 into MEM/WB. For each register:
    • Tell the name of the register
    • Tell how many bits each arrow going into the register represents, in order from top to bottom.
    • Tell what information is represented by each arrow going into the register.

    For example, the answer for the first register would be:

    IF/ID:
      32 bits; PC + 4
      32 bits; An instruction to be executed