Format and Content
The exam is non-cumulative in the sense that questions that appeared on the midterm exam will not be repeated on the final exam. However, the material covered in the second half of the course builds on and reiterates material covered in the first part of the course, so some overlap is inevitable.
The exam will consist of a mix of short answer questions and diagrams.
You do not need to memorize MIPS op codes, function codes, or control signal names. But you have to know what they all are and what they do.
The exam will be based on the Appendix C sections 7, 8, 9, and 11; Chapter 5 sections 1-5; Chapter 4 sections 1-8; the material related to Assignments 4-7; and class lectures.
For the final exam you should be able to:
- Name and give the widths for all the inputs and outputs of a memory system, given the memory’s width and height.
- Name, give the widths, and tell the meaning of all the inputs and outputs of an SRAM memory chip.
- Use flip-flops, a decoder, and gates to implement a small SRAM chip.
- Use tristate buffers in a memory system.
- Use a multiplexer to retrieve one word from a memory with a wider data bus than the word width.
- Draw a diagram showing how to construct a memory system from individual memory chips.
- Tell the differences between DRAM and SRAM memories.
- Identify the inputs, outputs, and the widths of the three ports of the MIPS register file.
- Draw a diagram showing the inputs, internal structure, and outputs of each module used in the design of the subset of the MIPS register file implemented in Assignment 5.
- Describe the levels of the memory hierarchy, and identify tradeoffs among the three parameters that determine each level’s position in the hierarchy relative to the CPU.
- Define lines and blocks.
- Calculate the expected hit ratio of a given cache design given a random pattern of memory acceesses.
- Explain temporal and spatial locality; explain how these phenomena affect the observed hit ratio attained by cache memory systems.
- Calculate the number of bits in each field of a memory address given various combinations of cache and main memory design parameters.
- Define direct-mapped, set-associative, and fully-associative cache designs.
- Tell how the way in which an array is accessed affects the cache hit ratio.
- Define cold start, capacity, and conflict misses.
- Define round-robin, least recently used (LRU), random, and optimal cache replacement algorithms.
- Explain the role of the V bit in cache designs.
- Draw and explain the implementation of a cache system.
- Define write through and write back cache designs, and discuss the pros and cons of each.
- Define cache coherency and how it can be dealt with.
- Draw a diagram that shows the PC register in the MIPS datapath, including all the input sources to it.
- Explain the timing of the single-cycle MIPS datapath.
- Identify all the control signals in the single-cycle MIPS datapath, and tell how each one would be set for each type of MIPS instruction.
- Explain the operation of all three types of I format instruction.
- Write or interpret Verilog expressions for MIPS instructions, including expressions involving sign extension, bit concatenation, and simple binary constants.
- Identify and draw diagrams showing the inputs, outputs, and connections among various elements of the MIPS single cycle datapath.
- Explain the rationale behind a pipelined implementation of the MIPS datapath.
- Calculate the speedup of a perfectly balanced pipelined datapath.
- Define structural, control, and data hazards in pipelined datapaths, and how to eliminate or minimize them.
- Tell the advantages and disadvantages of deeply pipelined datapaths.