Reading Assignment, Reference Material, and Resources
The assignment is based on the MIPS Register File design developed in Section C-8 of the textbook. The current reading assignment that covers this project is sections C-7 through C-11. The second exam will cover material from all 5 of these sections of Appendix C.
Assignment To Hand In
This is an optional assignment: you are responsible for understanding the material in this assignment, but you are not actually required to hand it in. Some people find that the time spent on the projects is too great for the increase in understanding that comes from doing them. If you sincerely feel that you can understand the material without doing the lab exercise, you don’t have to do it.
On the other hand, if you do submit the assignment, it will count as extra credit for the 10% of your course grade that is based on homework assignments. Thus, doing it could add approximately 2-4 points to your course average at the end of the term.
When you complete the project and have tested it carefully, submit it by sending email to me with “CS-343 Assignment 5 submission” in the subject line, and your name in the message body.
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Set up a Quartus project and Testbed for the assignment.
As covered in class on March 22, you will be implementing an 8 × 4 MIPS-like register file. It will be MIPS-like because (a) there will be no real register #0, there will be two read ports, and one write port.
Cretae a directory named Assignment_5 for the assignment. The top-level module should be named Register-File_Testbed.
The testbed will use switches 9..7 for Read Register #1 (RR1), switches 6..4 for Read Register #2 (RR2), and switches 3..1 for the Write Register number (WR). Switch 0 will be used as the RegWrite signal for register file. Use the four blue pushbuttons, Key 3..0, for the Write Data (WD) input. Connect the red LEDs to the switches, and connect Green LEDs 3..0 to the four Key inputs. (Note: the key inputs work backwards from what you expect: pressed gives a 0 and un-pressed gives a 1. The Using Quartus web page shows how to invert the inputs efficiently.
The testbed will also use the four seven-segment displays: Hex_3 and Hex_2 to display WR and WD respectively; and Hex_1 and Hex_0 to display the contents of the two registers being read from the two read ports. Hex_1 for R[RR1] (RD1), and Hex_0 to display R[RR2] (RD2).
You will also need an input pin for the clock for this project: use the DE1 50MHz clock. There will be some new warnings that will arise from this additional input, which you can ignore for now.
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Create a module for one register.
Use four D Flip-Flops with Enable (dffe) from the Quartus “storage” library for the register module. Four inputs (DataIn[3..0] provide the input data to the flip-flops; four outputs (DataOut[3..0]) supply the outputs from them. The Clock and Enable inputs go to all four flip-flops.
Save the register file as a symbol.
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Create the register file and save it as a symbol.
The inputs should be RR1[2..0], RR2[2..0], WR[2..0]; RegWrite; RD[3..0]; RD2[3..0]; and WD[3..0].
You will need a 3 × 8 multiplexer with an enable input to select the register to be written, and two 8 × 4 multiplexers for selecting which register to output from each read port.
Save the register file as a symbol and insert the symbol into the testbed.
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Test carefully.
The main benefit of actually doing this project is to make sure you understand the operation of the register file, which you can do by systematically testing your register file to be sure you can write any set of values into any registers, and then read out the expected values afterwards.