CS-343 Assignment 7
Due May 17th

Reading Assignment, Reference Material, and Resources

This assignment covers material from Chapter 4 of the textbook.

Questions

Put the answers to the following questions in the body of an email message (no attachments accepted). Use “CS-343 Assignment 7 submission” as the subject line. Be sure your name is in the email so you can receive credit.

You must submit this assignment by 5:00 pm on the due date to receive credit for it.

  1. Figure 4.1 shows two adders. Which one (the left one or the right one) is used to compute Branch Target Addresses?
  2. Explain why the output of the ALU is connected to both the Data Memory and the Register File.
  3. Where do the rs and rt instruction fields connect in Figure 4.7?
  4. Where do the R[rs] and R[rt] values connect in Figure 4.7?
  5. Construct a table with three rows, labelled R-type, lw, and sw, and three columns labelled RegWrite, MemWrite, and MemRead. Put a “1” in each cell where the indicated control signal would be true for the given op code, and a “0” in all the other cells.
  6. Why is there no “RegRead” control signal?
  7. For the Data Memory unit (Figure 4.8), assume the MemRead control signal signal is true, and answer the following questions:
    1. What is the op code of the instruction being executed?
    2. Which inputs and/or outputs are irrelevant when MemRead is true?
    3. Which inputs and/or outputs must be set to zero when MemRead is true?
  8. For the Data Memory unit (Figure 4.8), assume the MemWrite control signal signal is true, and answer the following questions:
    1. What is the op code of the instruction being executed?
    2. Which inputs and/or outputs are irrelevant when MemWrite is true?
    3. Which inputs and/or outputs must be set to zero when MemWrite is true?
  9. What is the ALU used for during the execution of beq instructions?
  10. What is the purpose of the MemToReg control signal?
  11. For which op code(s) will the MemToReg control signal be true?
  12. What is the purpose of the AND gate in Figure 4.17?
  13. What must the value of RegDst be for R-type instructions?
  14. What must the value of RegDst be for lw instructions?
  15. What must the value of RegDst be for sw instructions, and why?
  16. What must the value of RegDst be for beq instructions, and why?
  17. Define instruction latency.
  18. Define instruction throughput.
  19. What is the relationship between latency and throughput for the single-cycle datapath?
  20. What is the equation for the time it takes to execute a program?
  21. What determines the minimum clock period for the single-cycle datapath? (General answer.)
  22. Which one instruction determines the minimum clock period for the single-cycle datapath, and why?
  23. What is a perfectly balanced pipeline?
  24. What is the relationship between latency and throughput for a pipelined datapath?
  25. What is the maximum clock speed for a perfectly balanced n-stage pipelined datapath compared to a single-cycle datapath implemented using the same technology (same propogation delays for the gates)?
  26. What is the instruction latency for a perfectly balanced n-stage pipelined datapath compared to a single-cycle datapath implemented using the same technology?
  27. What is the instruction throughput for a perfectly balanced n-stage pipelined datapath compared to a single-cycle datapath implemented using the same technology?
  28. Define structural, data, and control hazards.
  29. Give an example of a structural hazard and tell how it can be eliminated.
  30. Give an example of a data hazard and give the name of the technique that can be used to minimize its effect.
  31. How are unavoidable data hazards dealt with in the MIPS instruction set architecture?
  32. Give an example of a control hazard and name a technique that can be used to minimize its effect.
  33. What type of hazard is register forwarding used for?
  34. Summarize how register forwarding works.
  35. What is the advantage of deep (many stages) pipelines?
  36. What is the disadvantage of deep pipelines?
  37. Write a sentence that summarizes the contents of all pipeline registers.
  38. If a pipeline has n stages, how many places does the system clock connect to?