Errata for Patterson and Hennessy’s
Computer Organization and Design, Third Edition

These errata are unofficial: they are only the ones found by my students and me. (Send me the ones you find, and I’ll add them to the list.) There is an official list posted on the book’s web site, which includes most, but not all, of the items given here, along with some others. The errata posted there have been reviewed by the authors, but the ones posted here have not.

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Christopher Vickery

A “Revised Printing” of the book was released in 2007. The words REVISED PRINTING appear in yellow letters inside a black bar at the top of the front cover. Many of the errata listed below were corrected in this printing. Some, however, were not. I’ve added a fixed tag to those items that are no longer in error in the revised printing edition of the book. If your copy of the book is not the Revised Printing, all of these errors apply to your copy.

I’ve marked errors that still exist in the Revised Printing with not fixed.

fixed Page 166, last two lines above “Negative Shortcut:” There should be a bar over the second X in the first two equations, and over the first X in the last one.

fixed Page 168: Refers to material “on the back end papers of this book” instead of “on the green card in the front of this book.”

fixed Page 168 Check Yourself: Choice 2 should be “ASCII string in C” with “string” in normal text font. Explanation: There is no string type in C, and wide strings can use 2 bytes per character. And choice 3 should use a capital S in the name of Java’s “String” type.

fixed Page 172 Figure 3.3: The <= symbols in the first two columns should all be < because you can’t get overflow if one operand is zero.

fixed Page 182 Fig 3.9 and its descripton on page 181, “Faster multiplier.” You need 31 adders, not 32, and Product0 is the rightmost bit of Mplier0.Mcand. What is labeled Product0 is actually Product1. And the leftmost input to the 31st (bottom) adder is Multiplier31.Mcand, not Multiplier3.Mcand.

fixed (sort of) Page 197 line 7: “… as noted in section .” is missing the section number, possibly because the reference is to the current section, Section 3.6. (The fixed version has the self-reference to Section 3.6.)

fixed (sort of) Page 197: Current IBM mainframes support both hex and IEEE-754 floating-point formats. (The fixed version mentions IEEE 755 when it means IEEE 754.)

fixed Page 209: Period missing at the end of the last sentence of the second paragraph.

fixed (on page 218) Page 217: Section 3.7, missing information: The IEEE-754 standard was developed by Intel and the Intel 8087 “numeric co-processor,” introduced in 1980, was its first implementation in hardware.

fixed Page 273, Exercise 4.10: The text of the question uses “I1” and “I2” to refer to the two different implementations. But the table refers to them as “M1” and “M2.”

fixed Page 278, Answer to Check Yourself 4.2, page 253: The answer should be “b (9.9 sec)” rather than “6.”

Page 290: “… sequential because their outputs depend on both their inputs and the contents of the internal state.” This doesn't say anything about why they are called “sequential,” even though the statement about sequential circuits is correct. Two fixes are (1) just to use the phrase about outputs depending on both inputs and state as the definition of sequential without saying why or (2) to explain that they are called sequential because the present state depends on the sequence of inputs instead of the current combination of input values … which would also explain why combinational circuits are called “combinational.”

not fixed Pages 300 through 314; Figures 5.11, 5.15, 5.17, 5.19, 5.20, 5.21, and 5.24: All of these figures label the output of the top-right Adder “ALU result.” It should be “Sum” and/or “Branch target,” as in Figure 5.9 on page 297.

fixed Page 302: The last line refers to the 3-bit ALU control instead of 4-bit.

partly fixed Figure 5.24 on page 314: The output of the AND gate should go to the Mux to the left of the one shown. The MemRead signal is chopped off on the right edge of the figure. It should connect to the line going into the bottom of the Data memory. The output of the adder in the upper right part of the diagram is the “Branch Target Address,” not the “ALU result.” Corrected figure is here. The Revised Printing fixes everything except the Adder for the Branch Address/

not fixedPage 318 Check Yourself: “Look at the control signal …” should be “Look at the control signals …” or “Look at the truth table …”

fixed Figure 5.27 on page 322: (1) The line connecting the output of the PC to the top input of the Mux controlled by ALUSrcA is missing. (2) The line connecting the Memory Data Register to the Mux controlled by MemtoReg is missing.

not fixedPage 326, line 11: “…PC source… should be “PCSource” (Reported by Neil Raza).

not fixedPage 328, line 10: “…IR[25:0]]…” should be “…IR[25:0]…” (Reported by Neil Roza.)

fixed Figure 5.38 on page 339: In State 4, the Memory Read Completion Step, RegDst should be 0 (the register number for writing is rt, bits 20:16 of the instruction). In that same state, MemtoReg should be 1 (data from the MDR is to be written to the register file). In the Revised Printing, this is Figure 5.37 on page 338.

fixed Page 351: “as we saw earlier in the Fallacies and Pitfalls (see page 350)” is a self-reference.

fixed Page 355: Question 5.11 Incrementing the index register by 1 in the second instruction is undoubtedly a bug: the value should be 4.

fixed Page 355: Question 5.12 “… described in Exercise 5.12 without …” should be “… described in Exercise 5.11 without ….”

fixed Figures 6.19 and 6.20 on page 397 The clock cycles are named CC 1 through CC 6 and then start over with CC 1. Going from 1 to 5 and then repeating would make sense, but not starting over after 6. And then in Fig. 6.28 on page 405 the cycles are named CC 1 through CC 9, which is inconsistent.

fixed Page 409: There should be a third input to the top Mux in Figure 6.30b. It should come from ID/EX. The same problem is repeated in Figs. 6.32 and 6.33.

not fixed The text on the last line of page 538 and the first line of page 539 refers to cache sizes of 4 to 512 KB in Fig. 7.30, but the sizes in the figure range from 1 to 128 KB. (But note that the revised printing has updated values for Figure 7.29.)

fixed Page 544 Figure 7.31: The labels for 1, 2, 4, and 8-way associativity are missing.

fixed Page 561: The solution for the Check Yourself on page 538 should be a-c-b-d rather than a-c-c-d.

partly fixed Page B-21 3 lines from the bottom: “specifies a variable register file that …” should be “specifies a variable, registerfile, that …” and “registerfile” should be in the monospaced font. (The variable name is still not in the monospaced font.)

fixed Page B-22 second bullet item from the top of the page: “z, representing unkown, …” should be “x, representing unknown, …”

fixed Page B-22, Test Yourself on the bottom of the page: Item 4 is “{{4{1'b1}},{4{1'b1}}}” but should be “{{4{1'b1}},{4{1'b0}}}”

not fixed Figure B.5.13 on page B-36: The caption says “three ALU control lines” but there are 4, and they are not labeled: the labels from left to right should be Ainvert, Bnegate, and Operation. (Operation is two bits.)

fixed The top part of Fig. B.6.2 on page B-42: There is an extra wrench handle in the middle. (This may be browser-specific.)

fixed Figure B.9.3 page B-61: The caption has a Yen sign where there should be an x, as in “4 x 2 SRAM” (This may be browser-specific.)

fixed Figure B.9.4 on the page following Figure B.9.3 also has a Yen sign instead of a x in the caption (should be “4M x 8 SRAM”). (This may be browser-specific.) And the page number at the bottom of the page, “(page 62)” should be “(page B-62)”.