Introduction

This laboratory session introduces two major items: (1) using the Platform Abstraction Layer (PAL) libraries to accomplish I/O tasks, and (2) using the EDIF design flow to generate “bit” files and downloading them to an RC200E kit for testing.

The applications itself is simple: use two seven segment displays to show the hexadecimal representation of the ASCII codes for characters typed on a keyboard.

Procedure

  1. Configure a new project for both Debug and EDIF design flows.

    Start DK, and re-open the workspace you created in Laboratory I. Create a new project in that workspace named Keybd2SevenSeg. How you spell the project name doesn’t matter much, but you can make things easier if you don’t put any spaces in the project name. In the New Project dialog box, select “Xilinx Virtex-II Chip,” which is the type of FPGA on the RC-200 kits.

    This step is optional, but it might make it easier to manage the project if you do it. From the Build menu, select Configurations, and delete all the configurations for this project except Debug and EDIF. (You will be deleting Release, VHDL, Verilog, SystemC, and Generic.)

    At this point it’s time to do some one-time setting up of DK itself. Under the Tools menu select Options, and make the following changes: go to the Tabs panel and click the indent spaces radio button, set the tab size to 2, and make sure auto-indent is checked. On the Format panel, select the output Category and change the font to Monaco, Courier, or Fixedsys. (Some of the output messages are tables that don’t line up right if you use a proportional font.)

    Set the Debug Configuration options.

    Be sure your new project is the active project. Go to Project -> Settings, select the Debug choice from the drop-down list, go to the Preprocessor tab, and add USE_SIM to the comma separated list of preprocessor defintions. Go to the Linker tab and add the following libraries as a comma separated list in the Object/library modules box: stdlib.hcl, pal_sim.hcl, sim.hcl, and pal_keyboard.hcl

    In the “Additional C/C++ Modules” box of the Linker tab, enter the following pathname: C:\Program Files\Celoxica\PDK\Software\Lib\PalSim.lib

    Other projects for this course will use the same settings for simulation except that pal_keyboard.hcl will only be used for keyboard projects, and other libraries may occasionally be added to the first list.

  2. Type in the program and simulate it.

    Be sure it works! Type in different scan codes and be sure they display the correct ASCII values. There is a chart with the scan codes in ms_scancodes.pdf.

  3. Set up the EDIF design flow and test the hardware.

    Select the EDIF build configuration, and enter the following values: add USE_RC200E to the list of preprocessor defintions; on the Chip panel, enter XC2V1000FG456-4 as the Part; on the linker tab, use stdlib.hcl, pal_rc200e.hcl, rc200e.hcl, and pal_keyboard.hcl as the libraries list. Finally, on the Build commands panel, view Commands and enter the following two lines: “cd EDIF” (no quotes) and “edifmake_rc200 Keybd2SevenSeg” again with no quotes, but if your project name has any spaces in it you have to put quotes around its name. Switch the view to Outputs, and enter the single line: EDIF.

    Build the project, making sure there are no errors or warnings, and use the FTU2 program to download and test your bit file.