Overview
This page summarizes the values you will need to specify when setting up various kinds of projects using the DK GUI.
The clock rates given are the maxima available for the hardware platforms, and a reasonable value for the simulation platform. The clock rate has to be 25175000 for projects that do video output to a VGA adapter or a touchscreen.
In addition to the required libraries listed, many projects need to link to additional libraries:
- pal_keyboard.hcl
- pal_mouse.hcl
- pal_console.hcl
- pal_framebuffer.hcl
- pal_framebuffer8.hcl
- pal_framebuffer16.hcl
There is also a top-level Pixel Streams library, pxs.hcl, for all Pixel Streams projects, and an additional platform-specific Pixel Streams library for each platform: pxs_rc10.hcl, pxs_rc200e.hcl, and pxs_rc300.hcl.
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| Platform | |||||
|---|---|---|---|---|---|
| Library | Simulation (Debug) | RC-10 | RC-200E | RC-300 | |
| FPGA Family: | Library | Xilinx Spartan-3/3L | Xilinx Virtex-II | Xilinx Virtex-II | |
| FPGA Part Number: | XC3S1500LFG320-4 | XC2V1000FG456-4 | XC2V6000FF1152-4 | ||
| Preprocessor: | USE_SIM, PAL_TARGET_CLOCK_RATE=1000000 |
USE_RC10, PAL_TARGET_CLOCK_RATE=48000000 |
USE_RC200E, PAL_TARGET_CLOCK_RATE=50000000 |
USE_RC300, PAL_TARGET_CLOCK_RATE=125000000 |
|
| Linker: Required Object/Library Modules: |
stdlib.hcl,pal_sim.hcl,sim.hcl | stdlib.hcl,pal_rc10.hcl,rc10.hcl | stdlib.hcl,pal_rc200e.hcl,rc200e.hcl | stdlib.hcl,pal_rc300.hcl,rc300.hcl | |
| Linker C/C++ Modules: |
C:\Program Files\Celoxica\ PDK\Software\Lib\PalSim.lib |
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| Build Commands Commands: |
cd EDIF edifmake_rc10 “project name” beep |
cd EDIF edifmake_rc200 “project name” beep |
cd EDIF edifmake_rc300 “project name” beep |
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| Build Commands Outputs: |
EDIF | EDIF | EDIF | ||