Click on the link above for information about the textbook for the course, how grades will be computed, the policy on homework, etc.
Click one of the links below to see what grades I have recorded for you so far this term. You need to send me a "code word" to access your grades. See Homework Assignment 1 for details.
Grades become permanent two weeks after they are posted, so be sure to check your grades regularly to be sure there haven't been any mistakes.
This is the second semester CS-343 is being offered. Initially, the table below shows what material I covered in the course last semester, which you may use to get an idea of what we will be doing this term. Sections with a green background are accurate, but sections with a red background are tentative or incomplete. I will change the background colors as the semester progresses and the table is updated.
| Class Number | Date | Topics | Assignments |
|---|---|---|---|
| 1 | January 27 | Course Introduction; Units of Measure. | Memorize:
Units of Measure Powers of Two Review Appendix A through section A.10. |
| 2 | January 29 | Encoding audio information in binary.
Encoding visual information in binary: CRT images.
Review of Digital Logic Fundamentals: Propagation delay (the time it takes a gate's output to change in response to changed value(s) at its input(s)). Fan-in (the number of inputs to a gate). Fan-out (the maximum number of loads to which an output may be connected while guaranteeing that the voltage on the output wire will not fall into the noise margin range. Truth tables, minterms, and constructing a sum of products network from a truth table. | Read Section A.11
Assignment 1 Due |
| 3 | February 3 | Algebraic and Karnaugh Map minimization of combinational networks. Gate-input count as a measure of network complexity. Combinational building blocks: full-adder, parallel adder, carry-lookahead logic. | Read Appendix B, pages 501-508 (minimization)
Review pages 469-470 (ripple-carry adder) Review Section 3.5.1, pages 76-78 (carry-lookahead logic) |
| 4 | February 5 | Carry Lookahead Logic continued; decoders and
multiplexors.
Sequential vs Combinational Logic | Read Sections A.12 and A.13
Assignment 2 Due Assignment 2 Solutions |
| 5 | February 10 | Unclocked and clocked Latches.
Finite State Machine Models. | Read Sections A.14 and A.15
Download and experiment with the Earle Latch. |
| February 12 | No Class (Lincoln's Birthday) | ||
| February 17 | No Class (President's Day) | ||
| 6 | February 19 | Level-sensitive and edge-sensitive circuits. | Read / Review pages 99 through 120
Assignment 3 Due Assignment 3 Solutions |
| 7 | February 24 | Flip-flop design: D, S-R, J-K, and T flip-flops.
Characteristic and Excitation Tables. State diagram, State encoding (full-encoded or "one-hot"). Mapping state names to state flip-flop values. | |
| 8 | February 26 | State Table: External Inputs; Present State; Next
State; State Flip-flop Inputs; External Outputs. Use excitation
table to determine flip-flop inputs.
Counter design using T flip-flops. Timer design using counter and controller. Designing the controller as a FSM. | |
| 9 | March 3 | FSM controllers and sequence detectors. | Read Chapter 6
Assignment 4 Due Assignment 4 Help Assignment 4 Solutions |
| 10 | March 5 | *** First Exam *** | |
| 11 | March 10 | Central Processing Units: The fetch-execute cycle. Instruction Set Architectures: RISC/CISC. The ARC ISA: Registers; memory addressing. | |
| 12 | March 12 | ARC ISA: Instruction encoding. ARC assembly language. High Level Language translation to assembly language. Call and arithmetic instruction encoding, including immediate operands. | |
| 13 | March 17 | Memory operations: load and store. Effective address (EA) calculations. Branch instructions; target address (TA) calculations using PC-relative addressing. Begin review of two's complement encoding. | |
| 14 | March 19 | Two's Complement review: Negative weight of sign bit; sign extension; conecting Simm13 field to the B bus. Design of one bit of an ALU that can do add, subtract, bitwise and, and bitwise or operations; using a multiplexor to select the result after performing all operations. Subtraction by complementing minuend and adding. Condition code logic, including overflow detection by comparing Cin and Cout of the sign bit. Lookup Table (LUT) implementation of an ALU bit slice. | Assignment 5 Due
Solution |
| 15 | March 24 | Datapath and Controller interactions: control signals and feedback. ARC CPU interface to memory: A Bus always supplies the address bits; B Bus supplies data when writing; C Bus receives data when reading. C Bus receives ALU Result or Memory Data, depending on the setting of the "Read" control signal. Register File design: Connections between the C Bus and flip-flop Rij (register i bit j). | |
| March 26 | *** Last Day to Drop *** | ||
| 16 | March 26 | ARC Register File Design: A, B, and C Bus Decoders. Tristate gates. Implementing a distributed multiplexor using a decoder and tristate buffers. Two sources of inputs to the bus decoders: the RD, RS1, and RS2 fields of the IR or internal Control Unit Logic. | Assignment 6 Due
Solution |
| 17 | March 31 | Hardwired Control Unit Design: Decoding states and Instruction Register fields; FSM for fetching and executing ld and st instructions. | Class Notes |
| 18 | April 2 | Review ARC Register File design and control: C Bus Mux, C Mux, C Decoder, A Mux, A Decoder, B Mux, B Decoder, flip-flops, AND gates, tristate buffers. ALU function codes. Barrel shifter implementation using multiplexors. Leftmost 27 bits of microinstructions generate the 24 control signals to the datapath and memory, analogous to the outputs listed below the horizontal line inside a state circle of a Moore state diagram or the "External Outputs" columns of a state table. Rightmost 14 bits of microinstructions select the next microinstruction to process, analogous to the logic associated with the arcs going from circle to circle in a state diagram, or the "Next State" columns of a state table. | Assignment 7 Due
Solutions |
| 19 | April 7 | ARC Control Word Sequences for ISA Fetch-execute cycle. | |
| 20 | April 9 | *** Exam 2 *** | |
| 21 | April 14 | Memory Hierachy (Registers, L1 cache, L2 cache, main memory, disk.) Frontside and Backside Busses. | Read Chapter 7 through page 268 |
| 22 | April 15 Tuesday | Constructing an MxN memory system from mxn RAM ICs. IC, RAM, ROM, volatile. | |
| April 16-24 | Spring Break | ||
| 23 | April 28 | ROM. Programmable Logic Devices: Programmable Logic Arrays (PLAs) have fuse matrices between inputs/inverters and AND gates and between AND gates and OR gates. Programmable Array Logics (PALs) are commonly used and have a fuse matrix only between the inputs/inverters and the AND gates. Programmable Read Only Memories (PROMs) are made from a decoder and a fuse matrix between the AND gates and the OR gates. EPROMS, EEPROMS, and Flash. | |
| 24 | April 30 | FPGAs; Software tools for FPGA development (demo). Cache: L2 read operation. | Assignment 8 Due
Solutions |
| 25 | May 5 | Cache Design | |
| 26 | May 7 | Direct, Associative, and Set-Associative caches.
Backside, Frontside, and System Busses. Device Controllers. | Read Chapter 8 through page 313.
Assignment 9 Due Solutions |
| 27 | May 12 | Bus Bandwidth (3 factors). Bus hierarchy and bus bridges. Memory Mapped I/O compared to Separate I/O address space. Device Controller functions. | |
| 28 | May 14 | Polled and Interrupt Driven I/O with a UART device controller. | Optional Extra Credit
Assignment Due
UART Handout |
| May 16-22 | *** Final Exam *** | ||