Procedure
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Log into your account and verify that it is working correctly.
Log into any one of the computers in A-205 or A-227 using your account name for this course, which consists of your last name and the digits "343" all as a single lower-case string. That is, if your name is "Avery Good Student", your account name is student343. Use the password given to you in class, and remember that you will be required to change it to something secure the first time you log in.
The names of the computers are:
A-205 A-227 birch apple cherry fir chestnut juniper elm mimosa ginkgo peach hemlock pine hickory plum spruce sycamore walnut If you are on campus, you can access the computers in room A-205 any time the department office is open; a secretary in the office will open the room for you if necessary. If you want to work from off campus and have a broadband Internet connection, you can access any of the computers by using the Remote Desktop Connection tool provided by Microsoft for both Windows and Macintosh computers. On Windows XP, it is located under . On Macintosh OSX is is under . Add .cs.qc.edu to one of the computer names listed above when prompted for the computer to connect to.
If you log in from off campus, you should use one of the computers in room A-227 so that people who are on campus can use the machines in A-205. (Only one person can be logged into a computer at a time.) The exception is Tues and Thurs between 5 and 6:30 when there is another class that uses the computers in A-227.
Once logged in, use Windows Explorer to verify that your ’My Documents’ directory contains a directory named ’My Projects.’ Create a new directory named ’Assignment_03’ in your My Projects directory. The new directory must be spelled and capitalized exactly as shown, including the underscore character, in order to receive credit for this assignment!
Log off the computer you used and log into another one. Verify that your Assignment_03 directory shows up on the second computer, indicating that your settings were successfully copied to the domain server (maple) when you logged off the first computer and that they were then copied to the second computer when you logged into it. If you have any problems with this step, contact Dr. Vickery for help before proceeding with the assignment.
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Download and fix a seven-segment display decoder.
I am providing you with a Verilog module that converts a 4-bit binary number (one hexadecimal digit) into a 7-bit binary code for lighting up the seven lights of a seven segment display. The file is: hex2sevenseg.v. Save a copy in your My Projects directory.
Examine hex2sevenseg.v and observe that the assign statement for segment G (the center one) is wrong. Study the rest of the module, and change the code for segment G so that it will light up for input values 2, 3, 4, 5, 6, 8, 9, A, B, D, E, and F. (The digits B and D are represented as lower-case letters to distinguish them from 0 and 8.) You will test your changes below.
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Create a Quartus project for the assignment.
Start the Quartus II application by clicking the icon on the desktop. For some reason, you might see a message referring to software licenses. This is normally a temporary problem, which you can fix by selecting “specify license file” from the pop-up message box or by going to . In either case, specify @oak.cs.qc.edu as the location of the license file. When you tab away from that text box, Quartus will check the license again, and you should see that the license type has changed from “No License” to “Full License.” If that doesn’t work, report the problem to Dr. Vickery and try another computer. Do not select the “30-day trial option,” “web license update,” or any of the other possible choices offered to you; they would just mess things up.
From the File menu, run the New Project Wizard. Select your Assignment_03 directory when asked where the project goes, and give the project the name calendar_next_state. Spell it just like that.
The next panel will ask you for files that you want to add to the project. Navigate to the copy of hex2sevenseg.v that you downloaded (and fixed!) and add it to the project. The file won’t be moved or copied anywhere, but Quartus will “know” that the file is part of the project.
On the family and device settings step, you will have to select the correct FPGA chip depending on which type of logic kit you are using. The three types of logic kits we have and their corresponding FPGA part numbers are shown in the table below. You will need to refer to the Connection type later on when you are ready to download your design from the PC to a logic kit.
Kit Type Chip Family Part Number Connection UP2 FLEX10K EPF10K70RC240-4 Byte Blaster UP3 Cyclone EP1C6Q240C8 Byte Blaster DE1 Cyclone II EP2C20F484C7 USB Blaster Note: This assignment uses a seven-segment display to show the next state outputs of the truth table, so you will have to use either a UP2 or a DE1 kit: the UP3 does not have any seven segment displays.
Skip past the EDA tool settings panel, and click Finish when the wizard shows the summary of the project.
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Build the top-level design.
From the File menu (or by clicking the new page toolbar button), create a new Block Diagram/Schematic file. Use the Symbol Tool (the button that looks like an AND gate) to add three input pins and seven output pins to the circuit. Look under when the Symbol panel opens up to find the pin symbols. Name the input pins IN_0, IN_1, and IN_2. Actually, you can name them anything (meaningful) you want to, but those are the names used in this assignment page. Save this file as calendar_next_state.bdf in your Assignment_03 directory. Since this is the first file in the project, that name and location will probably be the default.
Now you need to put a copy of the seven segment decoder into your top-level design. Proceed as follows:
- Open hex2sevenseg.v from within Quartus. If you haven’t already fixed the logic for segment G, now would be a good time to do that!.
- Select . If there is an error in the syntax of your logic for Segment G it will show up now and you will have to fix it to proceed.
- Go back to calendar_next_state.bdf and open up the Symbol Tool again. There should be a new top-level directory called Project there. Open it, and you should see the symbol for hex2sevenseg. Insert an instance of this symbol into your design, connect the outputs of the decoder to the seven output pins, and connect the top three inputs to the three input pins. Use the Symbol Tool to find the Vcc primitive (this gives a constant voltage equivalent to a logic value of 1), and connect it to the fourth input of the seven segment decoder.
You might find it helpful to turn on the Show Gridlines option under the View menu. If you make mistakes, select the wire piece you don’t want and delete it using the Del key. You might want to zoom in (Control-Spacebar) to do accurate work. Once a wire is connected to a pin, you should be able to move the pin and the wire will stay connected; that’s a way to make sure your connections are good.
Compile your top-level design. Your top level design is not complete yet (there is no logic for the next state truth table yet), but it’s time to do the first compilation: select or click the toolbar button with the right-pointing triangle on it (next to the grayed out Stop button), or just type Control-L.
Four tools should run: Analysis & Synthesis, Fitter, Assembler, and Timing Analyzer. There should be no errors but there will be some warnings that you can ignore for now.
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Make the pin assignments.
You have to tell Quartus which pin numbers on the FPGA correspond to the input and output pins in your diagram. Use the menu item to start this process. When the big panel opens up you should see a list of your three input and seven output pins in the “Node Name” column. Double-click in the cells of the “Location” column and type in the pin numbers to make the assignments.
The following links will take you to tables that show the pin numbers for the various switches, LEDs, and seven segment displays on the different logic kits:
For the UP2, it makes sense to use dip switches 1-3 for the inputs; for the DE1, use three of the four push buttons, keys 0-2. But remember that your inputs will be logically inverted when you use the pushbuttons: use the Symbol Tool to get inverters (“not” gates from the logic section) and put them between the input pins and the seven segment decoder.
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Recompile the design and configure the FPGA.
You had to compile the design once so the Assignment Editor could tell what pins you are using, and now you have to compile it again to get the assignments into the configuration file for the FPGA. Just press Control-L again to recompile. There should be no errors, and the only warnings should have to do with failure to specify what to do with unused pins and failure to specify capacitance values; both of these warnings can be ignored.
If you are using a UP2, be sure it is connected to the parallel port of the PC you are using through a ’Byte Blaster’ cable., and connect the power cube to the DC_IN connector on the UP2; two green LEDs should light up. Go to the Programmer panel. It’s the rightmost button on the top toolbar, or you can get to it using the Tools menu. If you don’t see “Byte Blaster [LPT1]” near the top of the panel that comes up, click the Hardware Setup button in the top left part of the panel and select it from the drop down menu.
If you are using a DE1, just connect it to one of the USB ports on the PC. It should start flashing the LEDs and seven segment displays when you connect it. There is a big red on/off button you might need to press to turn it on. Go to the Programmer panel. It’s the rightmost button on the top toolbar, or you can get to it using the Tools menu. If you don’t see “USB Blaster” near the top of the panel that comes up, click the Hardware Setup button in the top left part of the panel and select it from the drop down menu.
If your are using a UP3, you have made a mistake. There are no seven segment displays on the UP3!
In the Programmer panel, you should see a table with one row with the name calendar_next_state.sof in the File column. Click the box in the Program/Configure column for that file, and click the Start button on the left side of the panel. It should take a few seconds to program the UP2, less for the DE1.
Test your design.
Operate the three switches (UP2) or buttons (DE1) and verify that the seven segment display shows the numbers 0-7 correctly for each of the eight binary patterns 0002 through 1112. If not, make the necessary changes to fix the problems before proceeding.
It would be a good idea to exit Quartus and log off the computer at this point as a way of saving your work so far on the lab server computer, maple. Alternatively, you might save a copy of your Assignment_03 directory to a USB memory stick or, if you are very retro, a floppy disk.
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Implement the next state truth table.
Create another Block Diagram File. Add three input pins named PS_0, PS_1, and PS_2 and three output pins named NS_0, NS_1, and NS_2. Add the necessary inverters, AND gates and OR gates to implement the minimized next state truth table from Assignment 2. When you save the file, give it the name next_state_logic.bdf and be sure the “Add to Project” box is checked on the Save panel. Now use to make a symbol out of this module, insert a copy into the top level design between the input pins and the seven segment decoder, compile, download, and test your design.
Be sure to exit Quartus and log off the computer so you work is saved back to maple when you are finished.
Submit the Assignment
When you have completed testing the assignment, send me an email message telling me the project is ready for grading. I will get a copy of it from maple and test it.
The Subject line of your email must be CS-343 Assignment 3 and you must put your name in the body of the email message.
If you worked on the assignment with someone else, be sure to list the names of both contributers in the email message so you both get full credit. In this case, be sure to tell me which account has the final version of the project for me to look at.
Remember, it is perfectly all right to help each other to do the assignment. That’s the main reason I made the course discussion forum available. (Send me email if you don’t know the Username and Password for accessing the forum.) Just don’t exchange actual design files with each other; nobody learns anything if you do that.
Due Date The assignment is due by midnight, February 15. Do not submit the assignment unless you have verified that it works correctly using a logic kit in the lab. Having said that, you can get partial (half) credit for “trying.” Just say in your email that the assignment is incomplete, and I will look at your project, but I won’t try to run it.