CS-343 Assignment 2

Reading Assignments

Project Description

Development Steps

1. Before starting, be sure your account in the TREE lab is working according to the information in the TREE Lab Information web page and that you are familiar with the Using Quartus web page.
2. First, create a directory for this project directly under your My Projects directory in the lab. Use the name “Assignment 2” for this directory for this assignment.
3. Now open Quartus and use the New Project Wizard to set up your project. The top level directory, of course, must be the directory you just created. The name of the project is to be “carry-lookahead-unit,” and the name of the top-level entity is to be “carry-lookahead-testbed.” Use the FPGA part number from the DE1 I/O Pins web page when you get to that step of the wizard. Otherwise, you can use all the default values the wizard suggests.
4. Create a block diagram for the carry-lookahead unit. There should be an array of four input pins for the “A” inputs, a second array of four input pins for the “B” inputs, and a ninth input pin for the Carry In (Cin) to the entire unit. There should be an array of four output pins for the four carry out signals, C[4..1]. Save the block diagram as a symbol.
5. Create a second block diagram for the carry-lookahead testbed. Include input pins for all ten of the slide switches, and output pins for all the red LEDs and four of the green LEDs. Include a copy of the symbol for the carry-lookahead unit; connect switches 9:6 to the A 3:0 inputs; switches 5:2 to the B 3:0 inputs; switch 0 to the Carry In input, and the four outputs to Green LEDs 3:0. For feedback, also connect all ten slide switches to the corresponding red LEDs. Note that slide switch 1 will do nothing except to light up the corresponding red LED.
6. At this point, you should be able to compile your design, which will make the names of the I/O pins available for assigning to the proper DE-1 LEDs and switches.
7. All that remains is to implement the actual carry-lookahead logic. You will need an AND gate to produce the carry generate value for each pair of data inputs, and an OR gate, in parallel with the AND gates, for the carry propagates.

   Remember: the purpose of carry-lookahead logic is to eliminate the chaining of propagation delays across the bit positions (“slices”) of a parallel adder. Your logic networks for each of the four carry outputs may use only C0, the four carry-generate signals, and the four carry-propagate signals as their inputs. Do not use any other carry values or any other intermediate values to reduce the complexity of your implementation: you are designing for speed, not to reduce the number of gates.

   The Quartus logic primitives do not include the 5-input AND and OR gates you need for this assignment, but there are 6-input gates you can use instead. Connect the unused input of the AND gate to Vcc and the unused input of the OR gate to ground.

8. Once your assignment builds with no more than the expect two warning messages and no error messages, be sure to test it carefully to be sure it works. Update: if you install version 10 of the Quartus software for use off campus, you will receive two addional warnings about the classic timing analyzer, which you should ignore.

Submit